A Low Power 8-bit Magnitude Comparator with Small Transistor Count using Hybrid PTL/CMOS Logic
نویسندگان
چکیده
Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS Logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1‟s complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this paper and the proposed design has small power dissipation and less area over various supply voltages. Simulations based on BSIM 3V3 90nm CMOS technology. It shows an 8-b comparator of the proposed architecture only needs 154 transistors.
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